Computing systems have fueled the growth of AI. Improvements in deep-learning algorithms have inevitably gone hand-in-hand with the improvements in the hardware accelerators. Our ability to train increasingly complex AI models and achieve low-power, real-time inference depends on the capabilities of computing systems.
In recent years, the metrics used for optimizing and evaluating AI algorithms are diversifying: along with accuracy, there is increasing emphasis on the metrics such as energy efficiency and model size. Given this, researchers working on deep learning can no longer afford to ignore the computing system. Instead, the knowledge of the potential and limitations of computing systems can provide invaluable guidance to them in designing the most efficient and accurate algorithms.
This course aims to inform students, practitioners and researchers in deep-learning algorithms about the potential and limitations of various processor architectures for accelerating the deep learning algorithms. At the same time, it seeks to motivate and even challenge the engineers and professionals in the architecture domain to optimize the processors according to the needs of deep-learning algorithms.
Course contents: This course discusses AI acceleration on various computing systems, such as FPGAs, mobile/desktop GPUs, smartphones, ASICs, DSPs and CPUs. It explains the architecture of several commercial AI accelerators, viz., Microsoft's Brainwave, Qualcomm's Hexagon DSP, NVIDIA's desktop GPUs and Tensor cores, NVIDIA's Jetson GPU, Intel's Xeon Phi, Intel Habana Labs' Goya and Gaudi, Google's Tensor Processing Unit (TPU) version 1 to 4, Cerebras' Wafer Scale Engine, Alibaba's HanGuang Processor, Groq’s Tensor Streaming Processor (TSP), Untether’s TsunAImi Processor and Graphcore's Intelligence Processing Unit (IPU). Further, it discusses how Facebook optimizes AI services in its data center and how it optimizes its mobile app. The course also discusses several research-grade accelerators, such as memristor-based accelerators. Overall, the course teaches about AI accelerators at levels ranging from smartphone, desktop, server to data-center.
Apart from performance and energy metrics, this course also discusses hardware reliability and security techniques for deep-learning algorithms and accelerators. A few real-life applications that benefit from AI-accelerators are reviewed, such as autonomous driving and brain implants. The course draws from recent research papers to showcase the state-of-art in these fields. To make the course self-sufficient, a reasonable amount of background is presented on both computer architecture and CNNs.
This course is at the intersection of deep learning algorithms, computer architecture, and chip design, and thus, is expected to be beneficial for a broad range of learners.
Program Highlights
Certificate from IIT Roorkee
Certificate of Completion by IIT Roorkee
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Learn from IIT Roorkee professors and Industry Experts
Placement Eligibility Test
Proctored Exams with Deep Learning models with opportunity to get Placed
IIT Roorkee is ranked first among all the IITs AND 20th position globally in citations per faculty. Established in 1847, it's one of the oldest technical institutions in Asia. IIT Roorkee fosters a very strong entrepreneurial culture. Some of their alumni are highly successful as entrepreneurs in the new age digital economy.
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Instructor
Prof. Sparsh Mittal
Faculty at ECE Dept and Center for AI and DS
IIT Roorkee
Dr. Sparsh Mittal is currently working as an assistant professor at ECE Dept at IIT Roorkee, India. He is also a joint faculty at Center for AI and DS at IIT Roorkee. He received the B.Tech. degree from IIT, Roorkee, India and the Ph.D. degree from Iowa State University (ISU), USA. He has worked as a Post-Doctoral Research Associate at Oak Ridge National Lab (ORNL), USA and as an assistant professor at CSE, IIT Hyderabad. He was the graduating topper of his batch in B.Tech and his BTech project received the best project award. He has received a fellowship from ISU and a performance award from ORNL.
He has published more than 100 papers at top venues and his research has been covered by technical websites such as InsideHPC, HPCWire, Phys.org, and ScientificComputing. He is an associate editor of Elsevier's Journal of Systems Architecture. He has given invited talks at ISC Conference at Germany, New York University, University of Michigan and Xilinx (Hyderabad). In Stanford's list of world's top researchers, in the field of Computer Hardware & Architecture, he was ranked as number 107 (for whole career) and as number 3 (for year 2019 alone).
1.Four types of convolution strategies. Understanding their compute and memory characteristics and pros and cons; the deep learning frameworks that use these strategies
2.Comparison of architectural characteristics of Caffe/cuDNN/fbfft/cuda-convnet2 frameworks
1.Deep Learning techniques on FPGA; efficacy of FPGAs for binarized neural networks (BNNs)
Microsoft’s Brainwave Architecture for Deep Learning and the optimizations used such as pinning of parameters in the on-chip memory
1.Deep Learning on CPU: Scope and Motivation. Pros and cons of using CPUs in deep learning
Opportunities for CPUs in deep learning, such as low and medium-parallelism workloads, mobile platforms etc
2.Deep Learning on CPU: Case Studies
3.Deep Learning in Heterogeneous Computing: Case studies (ig.LITTLE-style asymmetric multicore processors (AMPs);
Wearable-handheld collaborative computing;
Mobile+cloud collaborative computing;
CPU+GPU heterogeneous computing on mobile devices
)
1.Introduction to NVIDIA Jetson and Comparison of architectural parameters of Jetson (TK1, TX1, TX2) with Intel UP, Raspberry Pi, DSP and FPGA
2.Deep Learning on NVIDIA Jetson: Study of some real-life applications mapped to Jetson platform, e.g., driver drowsiness detection, pill image recognition, local processing of CNN on a drone, drone racing, classifying weeds from drone imagery, detecting foot ulcers using a CNN, identifying faces of suspected people, etc.
1.Background on Pipelining, Superscalar and out-of-order execution
2.Background on big.LITTLE-style asymmetric multicore processors (AMPs)
3.Optimizing Facebook’s Machine Learning-based App on Smartphones: Challenges and opportunities faced in running Facebook app on smartphones of varied configurations (architecture/compute/memory-capacity)
1.Introduction to Memristors and processing-in-memory using Memristors
2.Memristor-based Deep Learning Accelerators (Accelerator Designs;
Techniques for Reducing Analog Overheads;
Pruning techniques;
Reliability techniques)
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Certification Guideline
You will be required to complete 100% of the course content within 90 days of enrollment to be eligible for the certificate.
Prerequisites
The candidate should have an idea of what is deep learning, especially the basics of CNNs and RNNs. Background in computer architecture or embedded-system is preferred, although not mandatory.
The candidate should have an idea of what is deep learning, especially the basics of CNNs and RNNs. Background in computer architecture or embedded-system is preferred, although not mandatory.
Someone who has successfully completed this course is expected to be able to solve problems more efficiently using some of the latest technologies in the industry.
Learners who have completed this course will be a perfect fit for VLSI, Semiconductor, or similar industries.
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